The present invention relates to programmable logic devices (xe2x80x9cPLDsxe2x80x9d), and more particularly, to efficient arrangement of resources that are used to interconnect various portions of a programmable logic device.
Programmable logic devices are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611.
There is continued interest in programmable logic devices with greater logic capacity. This calls for devices with larger numbers of regions of programmable logic. It also calls for logic devices with a greater number of interconnection conductors for making needed connections between the increased numbers of logic regions. It is important, however, to organize interconnection conductors judiciously so that they provide flexible interconnectivity, but do not begin to take up excessive amounts of space on the device, thereby unduly interfering with the amount of additional logic that can be included in the device. To accomplish this, it would be desirable to find ways to organize the interconnection resources on programmable logic devices so that the efficiency of utilization of the interconnection resources can be maximized. More interconnectivity could therefore be provided in the device to serve more logic in the device without simply adding more interconnection resources with the increased logic capability.
It is therefore an object of this invention to provide improved arrangements of interconnection conductors for programmable logic devices.
It also an object of the invention to provide programmable logic device conductor arrangements that can efficiently and flexibly interconnect larger numbers of programmable logic regions than previously possible.
These and other objects of the invention are accomplished in accordance with the principles of the present invention by providing arrangements for interconnection resources on programmable logic devices that have a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Each logic super-region in such a programmable logic device includes a plurality of regions of programmable logic and a plurality of inter-region interconnection conductors associated with the regions for conveying signals to and between the regions in that super-region. Each region may include a plurality of subregions of programmable logic. A typical subregion is programmable to perform any of several logical operations on a plurality of input signals applied to the subregion to produce an output signal of the subregion. Programmable logic connectors and local conductors may be associated with the regions for selectively bringing signals from the associated inter-region conductors to the subregions in that region for use as inputs. Interconnection groups may be used to selectively apply subregion output signals to the associated inter-region conductors.
A plurality of horizontal inter-super-region interconnection conductors may be associated with each row of super-regions for selectively conveying signals to, from, and between the super-regions in the that row. Similarly, a plurality of vertical inter-super-region interconnection conductors may be associated with each column of super-regions for selectively conveying signals to, from, and between the super-regions in that column.
The local conductors for selectively bringing signals into the region may include region-feeding conductors for bringing signals into the programmable logic region and local feedback conductors for making output signals of the region available as inputs to the region (i.e., recirculating signals within a given programmable logic region). The region-feeding conductors are programmably connectable to the inter-region interconnection conductors. The region feeding conductors convey signals from the inter-region interconnection conductors to the inputs of the subregions in the region. The local feedback conductors may be programmably connectable to the input of the subregions. The local feedback conductors supply feedback signals from the subregions to the inputs of the subregions.
Programmable interconnection groups may be used for various interconnection tasks such as turning signals traveling on inter-super-region and inter-region conductors onto other conductors and applying subregion output signals to the inter-super-region and inter-region conductors. The interconnection groups are typically organized so that they selectively direct signals from logic regions and inter-region and inter-super-region conductors to other inter-region and inter-super-region conductors.
The interconnection resources within each interconnection group may be divided into a plurality of interconnection blocks disposed on the programmable logic device in order to facilitate inter-connectivity, optimize use of the metallization resources, and increase the logic density of the device. A set of interconnection blocks may be associated with each programmable logic region for routing signals to and/or from an associated logic region, an adjacent logic region, or one or more inter-region or inter-super-region conductor signals. The interconnection blocks may arranged such that they handle certain interconnection functions. For example, each set of interconnection blocks may include vertical, horizontal, and local interconnection blocks that route signals to and from specific conductors and logic regions so that interconnection within the programmable logic device is facilitated. In addition, interconnection conductors may be distributed throughout the device to allow a more efficient use of the metallization resources and lessen the effects of cross-talk. This allows programmable logic devices to have increased logic density and to be easily scaled to smaller integrated circuit technologies.
Some of the programmable interconnection blocks, such as those near the periphery of the device, may also receive signals from input/output (xe2x80x9cI/Oxe2x80x9d) pins. These interconnection blocks may be used to route signals from the I/O pins to the appropriate conductors on the device. Some I/O pins may have dedicated interconnection blocks that route signals to one or more inter-super-region conductors and/or one or more inter-region interconnection conductors.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.